Key Responsibilities
- Develop and execute RNM AMS model for best in class PHYs.
- Make sure the quality of models reflects schemetics.
- Write and debug SystemVerilog/UVM compliant test cases
- Collaborate with design team to ensure design quality
- Expertise to understand analog blocks.
- 5+yrs relevant experience
- BS in EE or related field.
- Deep analog design expertise
- Knowledge of SystemVerilog, test environment and assertion coding
- Experience in verifying mixed signal IPs
- Experience with Formal verification with Jasper Gold or vc-formal
- Python/Perl/Tcl scripting for design verification